[Cuis-dev] [Vm-dev] Cuis on a RISC

[ken.dickey at whidbey.com]

On 2022-06-15 10:22, tim Rowledge wrote:
> A complication for a RiscV cog that I would anticipate from my fairly
> limited reading on RiscV is that the actual instruction set for any
> particular cpu can vary quite a lot because of the building-block
> nature of the specification. I hope it's not quite as confusing as it
> seems to me so far.

I expect RV64G to be pretty common.  Good as a baseline.

We can do without the vector stuff or 32 bit for quite a while, 
particularly until we get more real hardware.  ;^)

Good on ya,
-KenD