[Cuis-dev] [Vm-dev] Cuis on a RISC

[Gerald Klix]

I am sure Ken knows better than that.
After all he does things like this:
https://github.com/KenDickey/BeeYourself
Nevertheless I don't understand Ken's answer.
To make a story too long short: Obviously there never was a JIT version of the
opensmalltalk VM for the RiscV-architecture (I don't know to state this in a more explicit way).

Best Regards,
Gerald
On Jun 14 2022, at 5:21 pm, tim Rowledge <tim at rowledge.org> wrote:
>
>
>
> > On 2022-06-14, at 7:26 AM, ken.dickey at whidbey.com wrote:
> >
> > On 2022-06-14 06:37, Gerald Klix via Cuis-dev wrote:
> >
> >> I did not ask a specific enough question:
> >> "Wasn't there a RiscV JIT VM? AFAIR Eliott wrote something about that one."
> >
> > No. MIPS, ARM, and RISCV are all RISC architectures,
>
> Over the years I have noticed that a very large number of people seem to think that 'RISC architecture' maps to 'all RISC chips have the same instruction set'. It makes me shake my head sadly every time.
>
> tim
> --
> tim Rowledge; tim at rowledge.org; http://www.rowledge.org/tim
> "Virtual Memory" means never knowing where your next byte is coming from.
>

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